Skip to main content


Bihar State Power (Holding) Company Ltd. invites On-line Application for itself and its subsidiary companies namely North Bihar Power Distribution Company Limited (NBPDCL), South Bihar Power Distribution Company Ltd. (SBPDCL), Bihar State Power Transmission Company Ltd. 

(BSPTCL) & Bihar State Power Generation Company Limited (BSPGCL)
 from eligible candidates for appointment on the respective posts for its Head Offices and Field Offices as per the details given below:
1.Name of the post
- Junior Electrical Engineer (General)
 No of post- 450
 2.Name of the post-
 Junior Engineer (Mechanical)
 No of post- 22
 3.Name of the post-
 Junior Engineer (Electronics)
 For BSPGCL No of post- 9
 4.Name of the post-
 Assistant IT Manager 
No of post- 297
 5.Name of the post
- Assistant Operato
 No of post- 250 
6.Name of the post
- IT Manager
 No of post- 5
 Junior Electrical Engineer (General): 
Diploma in Electrical From a recognized Institute/College OR Be/B.Tech/B.Sc. (Engg.) in Electrical /Electrical & Electronics from recognized University/Institute approved by AICTE Junior Engineer (Mechanical):
 Diploma in Mechanical From a recognized Institute/College OR Be/B.Tech/B.Sc. (Engg.) in Mechanical from recognized University/Institute approved by AICTE
 Junior Engineer (Electronics):
 Diploma in Electronics OR Be/B.Tech/B.Sc. (Engg.) in Electronics from recognized University/Institute approved by AICTE
 Assistant IT Manager:
 MCA or full time BE/B.Tech (Computer Science/IT) from any Govt. recognized University/Institute 
Assistant Operator:
 10th or its equivalent from recognized Institution + ITI in Electrician Trade from any Institution IT Manager (Internal): MCA or BE/B.Tech/B.Sc. (Engineering) in Computer Science/IT from any Govt./AICTE recognized Institution/University HOW TO APPLY: Get More Jobs & Employment a




Popular posts from this blog

kurukshetra university syllabus engg 3rd ,4th sem

B.Tech 3rd Semester MATH-201 E MATHEMATICS - III L T P Theory : 100 Marks 3 1 - Sessional : 50 Marks Total : 150 Marks Duration of Exam : 3 Hrs. UNIT – I Fourier Series : Euler’s Formulae, Conditions for Fourier expansions, Fourier expansion of functions having points of discontinuity, change of interval, Odd & even functions, Half-range series. Fourier Transforms : Fourier integrals, Fourier transforms, Fourier cosine and sine transforms. Properties of Fourier transforms, Convolution theorem, Perseval’s identity, Relation between Fourier and Laplace transforms, Fourier transforms of the derivatives of a function, Application to boundary value problems. UNIT-II Functions of a Complex Variables : Functions of a complex variable, Exponential function, Trigonometric, Hyperbolic and Logarithmic functions, limit and continuity of a function, Differentiability and analyticity. Cauchy-Riemann equations, Necessary and sufficient conditions for a function to be analytic, Polar form of the …

kurukshetra university syllabus engg ist sem ,2nd sem

MATHEMATICS-I (COMMON FOR ALL BRANCHES) L T P Theory: 100 Marks 4 1 - Sessional: 50 Marks Total: 150 Marks During of exam : 3 Hrs. UNIT-I Applications of Differentiation : Taylor’s & Maclaurin’s series, Expansion by use of known series, Expansion by forming a differential equation, Asymptotes, Curvature, Radius of Curvature for Cartesian, Parametric & polar curves, Centre of curvature & chord of curvature, Tracing of Cartesian & polar curves (standard curves). UNIT – II Partial Differentiation & its Applications : Functions of two or more variables Partial derivatives, Total differential and differentiability, Derivatives of composite and implicit functions, change of variables. Homogeneous functions, Euler’s theorem, Jacobian, Taylor’s & Maclaurin’s series for functions of two variables (without proof), Errors and approximations, Maxima-minima of functions of two variables, Lagrange’s method of undetermined multipliers, Differentiation under the integral sign.…


B.TECH VIIth SEMESTER VLSI DESIGN (ECE-401E) L T P Theory : 100 3 2 - Sessional : 50 Time : 3Hrs UNIT 1 : NMOS & CMOS Fabrication Process Sequence, Basic electrical properties of NMOs & CMOS inverters, MOS Design Process : Stick Diagram & Design rules. UNIT 2 : Delay in MOS Circuits, Scaling of MOS Circuits, Some design examples, inverter, NAND gates, Multiplexer, Logic Function Block. Introduction to physical design of IC’s Layout rules & circuit abstractor, Cell generation, Layout environments, Layout methodologies, Packaging, Computational Complexity, Algorithmic Paradigms. UNIT 3: Placement : Partitioning, Floor planning, Placement. Routing : Fundamentals, Global Routing, Detailed Routing, Routing in FPGA’s. UNIT-4: Performance issues in Circuit Layout : Delay models, Timing Driven placement,TimingDrivenRouting,Via Minimization, Power Minimization, other issues. NOTE: The question paper shall have eight questions in all organized into four sections, each section ha…