Skip to main content

Education Research and Development Organization (ERDO) recruitment of Basic Tuition Teacher (BTT), District Education Controller (DEC) & Block Education Controller (BEC)

Education Research and Development Organization (ERDO) invites applications for the recruitment of Basic Tuition Teacher (BTT), District Education Controller (DEC) & Block Education Controller (BEC) vacancies

Application Fee
Post Name
Gen / OBC
SC / ST
PH
BTT
450/-
250/-
50/-
DEC
600/-
400/-
50/-
BEC
600/-
400/-
50/-
  • Payment Mode: Online/ Offline
Important Dates
  • Starting Date to Apply Online: 16-09-2018
  • Last Date to Apply Online: 18-10-2018
  • Last Date to Print Full Application: 25-10-2018
Age Limit (as on 01-07-2018)
  • Minimum Age for DEC: 24 Years
  • Minimum Age for BEC: 22 Years
  • Minimum Age for BTT: 21 Years
  • Maximum Age: 45 Years
Vacancy Details
Sl NoPost Name
Total
Qualification
1Basic Tuition Teacher (BTT)13,222
Any Degree, B.Ed/ B.T.C/B.P.Ed/ D.Ed/ J.B.T/ N.T.C/ P.T.T
2District Education Controller (DEC)29M.Ed, M.A education,M.Phil& Ph.D
3Block Education Controller (BEC)383
B.Ed/ B.T.C./ B.P.Ed/ D.Ed/ J.B.T/ N.T.C/ P.T.T
APPLY ONLINE   
https://www.erdo.in/apply-main.php

WEBSITE https://www.erdo.in/


BEST BLOG BY UNIQUE GROUP FOR SARKARI NAUKRI,www.uniqueinstitutes.org ,shailesh pathak

Comments

Popular posts from this blog

kurukshetra university syllabus engg 3rd ,4th sem

B.Tech 3rd Semester MATH-201 E MATHEMATICS - III L T P Theory : 100 Marks 3 1 - Sessional : 50 Marks Total : 150 Marks Duration of Exam : 3 Hrs. UNIT – I Fourier Series : Euler’s Formulae, Conditions for Fourier expansions, Fourier expansion of functions having points of discontinuity, change of interval, Odd & even functions, Half-range series. Fourier Transforms : Fourier integrals, Fourier transforms, Fourier cosine and sine transforms. Properties of Fourier transforms, Convolution theorem, Perseval’s identity, Relation between Fourier and Laplace transforms, Fourier transforms of the derivatives of a function, Application to boundary value problems. UNIT-II Functions of a Complex Variables : Functions of a complex variable, Exponential function, Trigonometric, Hyperbolic and Logarithmic functions, limit and continuity of a function, Differentiability and analyticity. Cauchy-Riemann equations, Necessary and sufficient conditions for a function to be analytic, Polar form of the …

kurukshetra university syllabus engg ist sem ,2nd sem

MATHEMATICS-I (COMMON FOR ALL BRANCHES) L T P Theory: 100 Marks 4 1 - Sessional: 50 Marks Total: 150 Marks During of exam : 3 Hrs. UNIT-I Applications of Differentiation : Taylor’s & Maclaurin’s series, Expansion by use of known series, Expansion by forming a differential equation, Asymptotes, Curvature, Radius of Curvature for Cartesian, Parametric & polar curves, Centre of curvature & chord of curvature, Tracing of Cartesian & polar curves (standard curves). UNIT – II Partial Differentiation & its Applications : Functions of two or more variables Partial derivatives, Total differential and differentiability, Derivatives of composite and implicit functions, change of variables. Homogeneous functions, Euler’s theorem, Jacobian, Taylor’s & Maclaurin’s series for functions of two variables (without proof), Errors and approximations, Maxima-minima of functions of two variables, Lagrange’s method of undetermined multipliers, Differentiation under the integral sign.…

syllabus of kUK ENGG ELECTRONICS 7TH ,8TH

B.TECH VIIth SEMESTER VLSI DESIGN (ECE-401E) L T P Theory : 100 3 2 - Sessional : 50 Time : 3Hrs UNIT 1 : NMOS & CMOS Fabrication Process Sequence, Basic electrical properties of NMOs & CMOS inverters, MOS Design Process : Stick Diagram & Design rules. UNIT 2 : Delay in MOS Circuits, Scaling of MOS Circuits, Some design examples, inverter, NAND gates, Multiplexer, Logic Function Block. Introduction to physical design of IC’s Layout rules & circuit abstractor, Cell generation, Layout environments, Layout methodologies, Packaging, Computational Complexity, Algorithmic Paradigms. UNIT 3: Placement : Partitioning, Floor planning, Placement. Routing : Fundamentals, Global Routing, Detailed Routing, Routing in FPGA’s. UNIT-4: Performance issues in Circuit Layout : Delay models, Timing Driven placement,TimingDrivenRouting,Via Minimization, Power Minimization, other issues. NOTE: The question paper shall have eight questions in all organized into four sections, each section ha…